Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications

This paper describes the architecture and components of a high-speed clock and data recovery (CDR) circuit. Fully differential CMOS circuits are prese nted for an integrated physical layer controller of a 622-Mb/s (OC-12) syst em, although the design can be used in other systems with clock speeds in t he 622-933-MHz range. Simulations and experimental results are presented fo r the building blocks including novel designs for a current-controlled osci llator (CCO) and a differential charge pump. The CCO is based on a two-stag e ring oscillator. It consists of parallel differential amplifier pairs whi ch reliably generate the necessary phase shift and gain to fulfill the osci llation conditions over process and temperature variations. Two test chips are implemented in 0.35-mu m CMOS. One contains partitioned building blocks of a phase-locked loop (PLL) which, together with an external loop filter, can be used for flexible testing and CDR applications. The other chip is a monolithic CDR with integrated loop filter. It exhibits a power consumptio n of 0.2 W and a measured rms clock jitter of 12.5 ps at 933 MHz.