nMOS reversible energy recovery logic for ultra-low-energy applications

We propose a new fully reversible adiabatic logic, nMOS reversible energy r ecovery logic (nRERL), which uses nMOS transistors only and a simpler 6-pha se clocked power. Its area overhead and energy consumption are smaller, com pared with the other fully adiabatic logics. We employed bootstrapped nMOS switches to simplify the nRERL, circuits. With the simulation results for a full adder, we confirmed that the nRERL circuit consumed substantially les s energy than the other adiabatic logic circuits at low-speed operation. We evaluated a test chip implemented with 0.8-mu m CMOS technology, which inc luded a chain of nRERL inverters integrated with a clocked power generator. The nRERL inverter chain of 2400 stages consumed the minimum energy at V-d d = 3.5 V at 55 kHz, where the adiabatic and leakage losses are about equal , which is only 4.50% of the dissipated energy of its corresponding CMOS ci rcuit at V-dd = 0 9 V. In conclusion, nRERL is more suitable than the other adiabatic logic circuits for the applications that do not require high per formance but low energy consumption.