Ultra CSP (TM) - A wafer level package

There has been a significant amount of work over the past five years on chi p scale packaging, The majority of this work has been an extension of conve ntional integrated circuit (IC) packaging technology utilizing either mire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale pack ages (CSP's) has resulted in a relatively high cost for these packages, Thi s paper reports a true wafer level packaging (WLP) technology called the Ul tra CSP(TM). One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This m akes the Ultra CSP ideal for both insertion at the end of the wafer tab as well as the facilitation of wafer level test and burn-in options. This is e specially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices a s a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSP's with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flas h memory, DRAM and other devices, The electrical and thermal performance ch aracteristics of the Ultra CSP package technology will also be discussed.