Wafer-level chip size package (WL-CSP)

Authors
Topper, M Fehlberg, S Scherpinski, K Karduck, C Glaw, V Heinricht, K Coskina, P Ehrmann, O Reichl, H
Citation
M. Topper et al., Wafer-level chip size package (WL-CSP), IEEE T AD P, 23(2), 2000, pp. 233-238
Citations number
12
Categorie Soggetti
Material Science & Engineering
Journal title
IEEE TRANSACTIONS ON ADVANCED PACKAGING
ISSN journal
15213323 → ACNP
Volume
23
Issue
2
Year of publication
2000
Pages
233 - 238
Database
ISI
SICI code
1521-3323(200005)23:2<233:WCSP(>2.0.ZU;2-M
Abstract
Size reduction is one of the main driving forces for packaging in nearly al l electronic applications, The interaction of size reduction with highest f unctionality and high reliability is also predominant for all microelectron ic systems. Therefore a synergism of optimal product design, smallest singl e chip package and board technology will give the best solution. Wafer leve l CSP will be the best solution for single chip packaging matching all requ irements for electronic systems and reducing total cost.