Parasitic resistance reduction in deep submicron dual-gate transistors with partially elevated source/drain extension regions fabricated by complementary metal-oxide-semiconductor technologies

Deep submicron dual-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with partially elevated source/drain (S/D) structures were fabri cated using complementary MOS (CMOS) technologies. In comparison with well- defined conventional MOSFETs, it is revealed that the drivability is apprec iably enhanced by the S/D elevation and, further, that a p-channel MOSFET g ains more from the SID elevation than an n-channel MOSFET. Investigation of the parasitic resistance is consistent with the results of the transistor characteristics.