Tuning strategies for global interconnects in high-performance deep-submicron ICs

Interconnect tuning is an increasingly critical degree of freedom in the ph ysical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses, widths and spacings in multi-la yer interconnect to simultaneously optimize signal distribution,signal perf ormance,signal integrity, and interconnect manufacturability and reliabilit y. This is a key activity in most leading-edge design projects, but has rec eived little attention in the literature. Our work provides the first techn ology-specific studies of interconnect tuning in the literature. We center on global wiring layers and interconnect tuning issues related to bus routi ng, repeater insertion, and choice of shielding/spacing rules for signal in tegrity and performance. We address four basic questions. (1) How should wi dth and spacing be allocated to maximize performance for a given line pitch ? (2) For a given line pitch, what criteria affect the optimal interval at which repeaters should be inserted into global interconnects? (3) Under wha t circumstances are shield wires the optimum technique for improving interc onnect performance? (4) In global interconnect with repeaters, what other i nterconnect tuning is possible? Our study of question (4) demonstrates a ne w approach of offsetting repeater placements that can reduce worst-case cro ss-chip delays by over 30% in current technologies.