Bitwidth analysis with application to silicon compilation

This paper introduces Bitwise, a compiler that minimizes the bitwidth - the number of bits used to represent each operand - for both integers and poin ters in a program. By propagating static information both forward and backw ard in the program dataflow graph, Bitwise frees the programmer from declar ing bitwidth invariants in cases where the compiler can determine bitwidths automatically. Because loop instructions comprise the bulk of dynamically executed instructions, Bitwise incorporates sophisticated loop analysis tec hniques for identifying bitwidths. We find a rich opportunity for bitwidth reduction in modern multimedia and streaming application workloads. For new architectures that support, sub-word data-types, se expect that our bitwid th reductions will save power and increase processor performance. This paper also applies our analysis to silicon compilation, the translatio n of programs into custom hardware, to realize the full benefits of bitwidt h reduction. We describe our integration of Bitwise with the DeepC Silicon Compiler. By taking advantage of bitwidth information during architectural synthesis, we reduce silicon real estate by 15 - 86%, improve clock speed b y 3 - 249%, and reduce power by 36 - 73%. The next era of general purpose a nd reconfigurable architectures should strive to capture a portion of these gains.