Design and analysis of built-in testers for CMOS switched-current circuits

This paper presents the design and analysis of a built-in tester circuit fo r MOS switched-current circuits used in low-voltage/low-power mixed-signal circuits/systems. The use of the tester can reduce the test length signific antly. The developed tester is comprised of a current comparator, a voltage window comparator, and a digital latch. The current comparator is required to have high-accuracy, low-power consumption, simple structure with small chip area, and moderate speed. Results show that the developed current comp arator circuit is developed with a small offset current, 0.1 nA, low power consumption, 20 mu W, and a layout area of 0.01 mm(2), where the circuit is simulated with the MOSIS SCN 2 mu m CMOS process parameters and 2 V supply voltage.