Reducing power by optimizing the necessary precision/range of floating-point arithmetic

Low-power systems often find the power cost of floating-point (FP) hardware prohibitively expensive. This paper explores ways of reducing FP power con sumption by minimizing the bitwidth representation of FP data. Analysis of several FP programs that: manipulate low-resolution human sensory data show s that these programs suffer no loss of accuracy even with a significant re duction in bitwidth. Most FP programs in our benchmark suite maintain the s ame output even when the mantissa bitwidth is reduced by half. This FP bitw idth reduction can deliver a Significant power saving through the use of a variable bitwidth FP unit. Our results show that up to 66% reduction in mul tiplier energy/operation can he achieved in the FP unit by this bitwidth re duction technique without sacrificing any program accuracy.