Glitch power minimization by selective gate freezing

This paper presents a technique for glitch power minimization in combinatio nal circuits. The total number of glitches is reduced by replacing some exi sting gates with functionally equivalent ones (called F-Gates) that can be "frozen" by asserting a control signal. A frozen gate cannot propagate glit ches to its output. Algorithms for gate selection and clustering that maxim ize the percentage of filtered glitches and reduce the overhead for generat ing the control signals are introduced. A power-efficient CMOS implementati on of F-Gates is also described. An important feature of the proposed metho d is that it can be applied in place directly to layout-level descriptions; therefore, it guarantees very predictable results and minimizes the impact of the transformation on circuit size and speed.