Memory modeling for system synthesis

We present our methodology for developing models of on-chip SRAM memory org anizations. The models were created to enable the quick evaluation of energ y, area, and performance of different memory configurations considered duri ng synthesis. The models are defined in terms of parameters, such as size a nd mode of operation, which are known at synthesis time. Our methodology do es not require knowledge of the underlying memory circuitry and provides mo dels with average percentage errors within 8%. We examine the importance of the different parameters in the models to reduce the time required to deve lop the models. We found that only ten different memories from a large span of possible memory sizes are needed to obtain reasonably accurate models, with average errors within 15%. In this paper, we present our modeling meth odology, discuss the important aspects in developing the models, and examin e the parameters necessary in creating accurate models quickly and easily.