A self-timed real-time sorting network

High-speed networks are expected to carry traffic classes with diverse qual ity of service (QoS) guarantees. For efficient utilization of resources, so phisticated scheduling protocols are needed; however, these must be impleme nted without sacrificing the maximum possible bandwidth. This paper present s the architecture and implementation of a self-timed real-time sorting net work to be used in packet switches that support a diverse mix of traffic. T he sorting network receives packets with appropriately assigned priorities and schedules the packets for departure in a highest-priority-first manner. The circuit implementation uses zero-overhead, self-timed, and self-precha rging domino logic to minimize the circuit latency An experimental sorting network chip has been designed using the techniques described in this paper to support 10-Gb/s links with ATM-size packets.