D0 MUON READOUT ELECTRONICS DESIGN

The readout electronics designed for the DO Muon Upgrade [1] are descr ibed. These electronics serve three detector subsystems and one trigge r system. The front-ends and readout hardware are synchronized by mean s of timing signals broadcast from the DO Trigger Framework. The front -end electronics have continuously running digitizers and two levels o f buffering resulting in nearly deadtimeless operation. The raw data i s corrected and formatted by 16-bit fixed point DSP processors. These processors also perform control of the data buffering. The data transf er from the front-end electronics located on the detector platform is performed by serial links running at 160 Mbit/s. The design and test r esults of the subsystem readout electronics and system interface are d iscussed.