Elevated source drain devices using silicon selective epitaxial growth

Elevated source drain (ESD) structure in deep submicron metal oxide semicon ductor field effect transistors (MOSFETs) can help reduce parasitic series resistance and simultaneously achieve shallow contacting junctions to minim ize short channel effects. A self-aligned ESD structure in conventional com plimentary metal-oxide-semiconductor processing can be achieved using silic on selective epitaxial growth (SEG). A robust low thermal budget high quali ty SEG process using a commercial rapid thermal chemical vapor deposition r eactor for ESD formation has been demonstrated. The preclean sequence prior to SEG is the key to achieve facet-free epitaxy. Low line-to-line leakage: confirms the high selectivity to nitride and oxide. The growth on exposed polysilicon (poly) gates leads to gate linewidth widening and lower Sate sh eet resistance. ESD parametric data suggest that the well doping needs to b e optimized to counter the slight increase in n + -p diode leakage. Capacit ance-voltage simulations indicate that the gate to drain capacitance initia lly decreases and then increases with SEG thickness. (C) 2000 American Vacu um Society. [S0734-211X(00)13503-6].