Intrinsic limitations on device performance and reliability from bond-constraint induced transition regions at interfaces of stacked dielectrics

The substitution of deposited alternative Sate dielectrics for thermally gr own SiO2 in aggressively scaled complementary metal-oxide-semiconductor dev ices requires separate and independent processing steps for (i) the oxidati on of the Si substrate to form the Si-dielectric interface and (ii) the dep osition of thin film dielectric. Ultrathin plasma-oxidized Si-SiO2 interfac e layers which contribute approximately 0.3-0.4 nm to the overall electrica l oxide thickness have been integrated into devices with Si nitride, Si oxy nitride, and Ta2O5 alternative dielectrics. This article proposes an analog y between (i) microscopically inhomogeneous bulk glass alloys such as GeSex with 1 < x <2, and (ii) interfaces included in these composite gate dielec tric-semiconductor structures including, for examples, the Si-SiO2 and inte rnal dielectric SiO2-Si3N4 interfaces. Scaling relationships for bond defec t states applied initially to microscopically inhomogeneous glasses and thi n films are applied here to interfaces in stacked gate dielectrics. (C) 200 0 American Vacuum Society.