A differential CMOS edge-triggered flip-flop is proposed that employs a pai
r of cross-coupled inverters, providing fully static operation. The edge-tr
iggering operation is achieved by a narrow pulse, produced by the clock sig
nal and its inverted delayed version. The proposed flip-flop exhibits signi
ficant power savings of up to 25%. when compared with other static differen
tial flip-flop circuits, maintaining its speed advantage for different powe
r supply voltages and data activity rates. It also requires only 12 transis
tors resulting in a reduced transistor count. Moreover. unlike the existing
differential circuits, it has the ability to operate under a reduced swing
clock signal, without static power dissipation.