Approach to the design of low-voltage SC filters

A design approach for low-voltage SC filers to be implemented in standard C MOS processes is presented. It is based on simple building blocks which are a clock booster and an SC integrator which uses a single-input amplifier i nstead of the traditional differential-input amplifier. To validate the pro posed approach, a fourth-order elliptic SC low-pass filter was designed usi ng a 1.2 mu m CMOS process and 1,5V power supply. The measured frequency re sponse accurately agrees with the simulated one in which an infinite-gain a mplifier was considered. When the power supply is set to 1.5V. the filter h as a power consumption of 400 mu W and occupies a silicon area of 0.8mm(2).