Three alternative architectures of digital ratioed compressor design with application to inner-product processing

Inner-product calculations are often required in digital neural computing. The critical path of the inner product of two binary vectors is the carry p ropagation delay generated from individual product terms. Three alternative architecture for arranging digital ratioed compressors are presented, to r educe the carry propagation delay in the critical path wherein an improved design of a 3-2 compressor is used to serve as the basic building element. The carry propagation delay estimation for the there architectures is also derived and compared. The theoretical analyses and Verilog simulations both indicate that one of the architectures presented might offer a suboptimal solution for summing the individual product terms in the inner-product comp utation. Furthermore, a real chip for the sub-optimal architecture was fabr icated and fully tested. The testing results prove the correctness of its f unctions and performance.