The paper examines the design issues of decoders, including the primitive o
peration (POP) translation strategies and the decoding rules, for CISC supe
rscalar processors to exploit a higher degree of parallel execution. Attent
ion is focused on the x 86 instruction set because of its popularity. There
are two different approaches regarding POP translation strategies: one is
to merge the address generation into load/store operations, and the other i
s to translate the isolated address generation operations. Simulation resul
ts show that, in high issue-rate decoders, the latter strategy improves the
performance by 20 to 25 %. Furthermore, considering the tradeoffs between
the hardware cost and performance, a cost-effective decoding rule suitable
for current commercial programs is recommended.