Cell-based implementation of radix-4/2 64b dividend 32b divisor signed integer divider using the COMPASS cell library

A high-speed 64b/32b integer divider using the digit-recurrence division me thod and the on-the-fly conversion algorithm, is presented. A fast normalis er is used as the preprocessor of the proposed integer divider. To reduce m aximum division time, the proposed divider uses radix-4/2 division, instead of the traditional radix-2 division. On-the-fly quotient adjustment is als o realised in the converter module of the divider. The entire design is wri tten in the Verilog hardware description language using the COMPASS 0.6 mu m 1P3M cell library (V3.0), and then synthesised by SYNOPSYS. Finally a rea l chip is fabricated and fully tested. The test results are very impressive . A performance evaluation of a 128b/64b signed integer divider using the s ame design methodology is also included in this study.