The impacts of control gate voltage on the cycling endurance of split gateflash memory

In this paper, the "erase" degradation in program/erase (P/E) cycling endur ance of split-gate flash memory has been investigated. It is found that inc reasing the control-gate (CG) voltage (V-CG) during erasing can slow down t he "window closure" of cycling endurance since a higher V-CG can "push" the FG potential into gradual part of IRead-out - V-FG curve and in turn reduc e the read-out current degradation. Moreover, the experimental results show that scaling down the gate oxide thickness under FG can effective reduce t he IRead-out degradation in cycling endurance test.