A novel simplified process for fabricating a very high density P-channel trench gate power MOSFET

A novel simplified fabrication method of a very high density p-channel tren ch gate power MOSFET using four mask layers and nitride/TEOS sidewall space rs is realized. The proposed process showed an improved on-resistance chara cteristics of device with increasing cell density and the cost-effective pr oduction capability due to the less number of processing steps. By using th is process technique, a remarkably increased high density (100 Mcell/inch(2 )) trench gate power MOSFET with a cell pitch of 2.5 mu m could be effectiv ely realized. The fabricated device had a low specific on-resistance of 1.1 m Omega . cm(2) with a breakdown voltage of -36 V.