Switching well noise modeling and minimization strategy for digital circuits with a controllable threshold voltage scheme

This paper describes a new model for characterizing the switching well nois e suited for application-specific integrated circuits (ASIC's) of gate-arra y and standard-cell-style digital circuits. A new technique employed in thi s work is to incorporate the controllable threshold voltage scheme, necessi tated by the recent demand for low power designs, into the well noise analy sis. The propagation process of the noise through the well is fully analyze d, providing practical approximation and reduction techniques of the peak n oise value, which are of use to estimate the possible maximum noise value a t the early stage of the design. SPICE simulation results are shown to demo nstrate and verify the effectiveness of these techniques in reducing the we ll noise and the precision of the peak approximation. A novel design method ology to optimize both area and noise is proposed based on the stochastic m odeling of the multiple noise sources and their superposition effects.