CMOS high speed interpolators based on parallel architecture

In our project, we design a serial of interpolators, including twice, four- time and eight-time data interpolators. In our design, we adopt the paralle l architecture to realize the circuits to make the speed of twice (x2), fou r-time (x4) and eight-time (x8) interpolators reach about 50, 40 and 30 MHz respectively. We use 0.8 mu m double-metal single poly CMOS technology to fabricate our chips. To balance speed and accuracy of the interpolators, we use eighth-order Sinc function as interpolation function, and utilize the symmetry of Sine function to simplify the structure of interpolator. The in terpolating error is about 1.5%. Operating power voltage is 5 v and power d issipation is 70mwatts at 50 MHz. The chips of our design are suitable for high speed digital signal processing, image processing and other applicatio ns.