This paper presents architectural and algorithmic approaches for achieving
high-speed CORDIC processing in both of the two operating modes: vectoring
and rotation. For vectoring mode CORDIC processing, a modified architecture
is proposed, which aims at reduction of computation time by overlapping th
e stages for redundant addition and selection of rotation direction. In add
ition, a novel rotation direction prediction scheme for rotation mode CORDI
C is presented. The method is based on approximation of the binary angle in
put to a number with the arctangent weights (tan(-1) 2(-i)). The implementa
tion is designed to keep the fast timing characteristics of redundant arith
metic in the x/y path of the CORDIC processing. The characteristics are ana
lyzed with respect to latency time and area, and compared with those obtain
ed by conventional CORDIC implementations. The results show that the propos
ed techniques reduce not only the block latency but also the overall comput
ation time. Thus, they achieve higher throughput in pipelining.