Analysis of leakage currents and impact on off-state power consumption forCMOS technology in the 100-nm regime

Off-state leakage currents have been investigated for sub-100 nm CMOS techn ology. The two leakage mechanisms investigated in this work include convent ional off-state leakage due to short channel effects and gate leakage throu gh ultrathin gate oxides. The conventional off-state leakage due to short c hannel effects exhibited the similar characteristics as previously publishe d; however, gate leakage introduces two significant consequences with respe ct to off-state power consumption: 1) an increase in the number of transist ors contributing to the total off-state power consumption of the chip and 2 ) an increase in the conventional off-state current due to gate leakage nea r the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications o f the National Technology Roadmap for Semiconductors for gate oxides as thi n as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applicat ions may be limited to an oxide thickness of 1.8 to 2.0 nm in order to mini mize the off-state power consumption and maintain an acceptable level of ch arge retention. The analysis in this work suggests that reliability will pr obably limit silicon oxide scaling for high performance applications wherea s gate leakage will limit gate oxide scaling for low power and memory appli cations.