Elevated source/drain by sacrificial selective epitaxy for high performance deep submicron CMOS: Process window versus complexity

The continuous downscaling of CMOS devices aims at cost reduction and perfo rmance improvement. Process development constantly faces new constraints an d integrates breakthroughs to overcome them. In deep submicron CMOS generat ions, scalability is in part limited by conflicting needs for shallow silic ided junctions and low junction leakage. Both requirements can be met using elevated source/drain (S-E/D) architecture. Although this solution has lon g been established, its avoidable extra complexity has delayed its introduc tion in industrial mainstream technologies. However, as device scaling cont inues, process windows are reducing critically. As a result, S-E/D architec ture is attracting a growing interest. This paper reports on a 0.18 mu m CM OS technology featuring S-E/D made with sacrificial selective epitaxy, This technology is examined from the standpoints of manufacturability and perfo rmance improvement. In contrast to most S-E/D approaches, the selective epi taxy is done after junction formation, resulting in increased process windo w Our S-E/D process leads to de and rf device performance enhancements. Nev ertheless, the same functionality gains were achieved by a fine-tuning of t he reference conventional low-cost process. Process window reduction will r equire S-E/D for generations below 0.13 mu m.