A cost effective embedded DRAM integration for high density memory and high performance logic using 0.15 mu m technology node and beyond

In this paper, a 0.15 mu m embedded DRAM technology is described which prov ides a cost-effective means of delivering high bandwidth, low power consump tion, noise immunity, and a small foot print chip. The key technologies for high performance transistors are dual thickness gate oxide, dual work-func tion gate with Si3N4 capped Ti polycide, and selective Co silicidation of s ource/drain diffusion by Si3N4 liner. In order to increase the memory cell efficiency, all memory cell contacts in DRAM arrays are formed by self-alig ned contact (SAC) etching. Low temperature Al2O3 stacked cell capacitor wit h hemispherical grain (HSG) makes it possible to realize the sufficient sto rage capacitance in DRAM arrays and the high performance transistor. The CM P planarization of interlayer dielectric enlarges the depth of focus for li thography and enables the multilevel metallization. These integration techn ologies can be fairly extendible to the future embedded DRAM in 0.13 mu m t echnology node and beyond.