A simple phase compensation technique with improved PSRR for CMOS opamps

A simple phase compensation technique with improved power supply rejection ratio (PSRR) for CMOS opamps is proposed. This technique is based on feedin g back a current proportional to a derivative of the voltage difference bet ween an output and an input, and does not require a common-gate circuit or a noise-free bias for the circuit. The proposed technique requires only two additional transistors, which are connected to the differential pair of tr ansistors in a cascade manner, and the compensation capacitor is connected to the source node of the additional transistor. Experimental results show an improvement of more than 20 dB in the PSRR at high frequencies, comparin g the technique with a Miller compensation. This technique also improves th e unity gain frequency and the phase margin from 0.9 MHz. and 17 degrees to 1.8 MHz and 44 degrees for 200 pF load capacitance, respectively.