A new clock routing algorithm using link-edge insertion for high performance IC design

As the clock skew is one of the major constraints for high speed synchronou s ICs, it must be minimized in order to obtain high performance. But clock skew minimisation may increase the total wire length; therefore, clock rout ing is performed within the given skew bound. Clock routing under the speci fied skew bound can decrease the total wire length. A new efficient algorit hm for bounded clock skew routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevents the total wire l ength from increasing. Not only the total wire length and delay time minimi zation algorithm using the new merging point relocation method but also the clock skew reduction algorithm using link-edge insertion technique for a p air of nodes whose delay difference is large is proposed. The proposed algo rithm constructs a new clock routing topology which is a generalized graph model, while most previous methods use only tree-structured routing topolog y. A new cost function is designed in order to select two nodes for link-ed ge addition. Using this cost function, delay difference or clock skew is re duced by connecting two nodes whose delay difference is large and distance is small. Furthermore, routing topology construction and wire sizing algori thm is used to reduce the clock delay. The proposed algorithm is implemente d in C programming language. The experimental results show that the total w ire length can be reduced under the given skew bound.