A second-order sigma-delta modulator with a gain scaling of ADC and a simple multibit DAC

A second-order sigma-delta modulator with a 3-bit internal quantizer Featur ing a gain scaling of an internal ADC and a very simple internal DAC! has b een designed and implemented in a, 0.8 mu m double-poly double-metal CMOS p rocess. We improved the performance of the modulator with the gain scaling of a 3-bit internal ADC: and design of the internal error-free DAC with usi ng simple logic gates. The specification of each component is determined fo r the modulator to have 14-bit resolution by time based modeling and the de signed components satisfy the required specifications. The peak SNR of 87 d B and dynamic range of 87 dB were achieved at a clock rate of 2.816 MHz for 22 kHz baseband. The measured results show that the fabricated modulator L ower SNR by 14 dB than that of the simulation due to the non-ideal input so urce and the disregarded error factors in the modeling such as the voltage variable capacitors etc.