Analysis of integrated circuit fault data using generalized linear models

Fault data for integrated circuits manufactured on silicon wafers are usual ly presented using wafer maps to indicate the spatial distribution of defec ts. This paper shows how this type of spatial data can be analyzed under th e framework of generalized linear models. This provides a systematic method for monitoring the quality of a manufacturing process, and identifying fau lt sources with assignable causes that may possibly be eliminated with proc ess improvement as a result. We consider models that account for different spatial patterns and, in particular, the observed phenomenon that the fault s are distributed non-uniformly across the wafer. Furthermore, we demonstra te how designed experiments can be used in optimizing the setting of import ant process parameters. Copyright (C) 2000 John Wiley & Sons, Ltd.