SIZE EFFECT ON THERMAL CONDUCTION IN SILICON-ON-INSULATOR DEVICES UNDER ELECTROSTATIC DISCHARGE (ESD) CONDITIONS

Previous experimental work has shown degradation in the electrostatic discharge (ESD) failure voltage for silicon-on-insulator (SOI) devices compared to that of devices made horn bulk silicon substrates. Unders tanding of this trend requires simulations of temperature fields in SO I devices using accurate thermal property values. The present work pre dicts the in-plane lattice thermal conductivity of thin silicon films at temperatures up to 1000 K considering the size effect due to phonon -boundary scattering. For silicon layers thinner than 0.2 mu m, a sign ificant reduction in the thermal conductivity is expected even at temp eratures as high as 700 K. A compact expression for the thermal conduc tivity of thin silicon films can be readily used in device simulations . Temperature field predictions for a simplified SOI device show the i mpact of the size effect and motivate discussion of its implications f or ESD buffer design.