A vertical MOS-gated Esaki tunneling transistor in silicon

For the first time a vertical, MOS gated tunneling transistor in silicon is fabricated. The necessary sharp doping profile structure is created by mea ns of MBE. Pronounced transistor action due to Esaki tunneling is demonstra ted at room temperature. At a low supply voltage of -0.2 V a current gain o f three magnitudes with saturation behaviour is achieved. MOS-gate, low sup ply voltage and exponential current increase make this device attractive fo r ULSI applications. (C) 2000 Elsevier Science S.A. All rights reserved.