DIAGNOSTIC FAULT SIMULATION FOR SYNCHRONOUS SEQUENTIAL-CIRCUITS

In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is first presented. A distributed diagnostic f ault simulator is then presented based on the sequential algorithm to improve the speed of the diagnostic process. In the sequential diagnos tic fault simulator, the number of fault-pair output response comparis ons has been minimized by using an indistinguishability fault list tha t stores the faults that are indistinguishable from each fault. Due to the symmetrical relationship of the fault-pair distinguishability, fa ult list sizes are reduced. Therefore, the different diagnostic measur es of a given test set can be generated very quickly using a small amo unt of memory. To further speed up the process of finding the indistin guishable fault list for each fault, a distributed approach is propose d and developed. The major idea for this approach is that each process or constructs the indistinguishable fault lists for a certain percenta ge of faults only. Experimental results show that the sequential diagn ostic fault simulator runs faster and uses less memory than a previous ly developed one and that the distributed algorithm even achieves supe rlinear speedup for a very large sequential benchmark circuit, s35932. To the authors' knowledge, no distributed diagnostic fault simulation system for sequential circuits has been proposed before.