Developing design rules to avert cracking and debonding in integrated circuit structures

In an integrated circuit, stresses come from many sources (e.g., differenti al, thermal expansion and electromigration). The circuit structures are nev er perfect, possibly containing crack-like flaws. The stresses may drive th e pre-existing cracks to grow and cause circuit failure. We explore a fract ure mechanics approach to formulate design rules to avert crack growth. We adopt a strategy based on two attributes of integrated circuits. First, hig h tensile sress is generated by internal misfit, and is therefore confined in small regions with size comparable to the feature dimension. Second, the fabrication process is controlled down to the individual features, so that the pre-existing cracks are expected to be smaller than the feature sizes. Instead of considering pre-existing crack, we consider all possible pre-ex isting cracks, and require that none of them should grow. Such a no-crackin g condition is independent of the nature of pre-existing cracks; rather, it depends on parameters that define a circuit structure, such as the feature size and the aspect ratios of the geometry. Furthermore, the stress singul arity at sharp corners in a circuit structure does not cause any particular difficulty. We illustrate these ideas with elementary examples involving b lanket films and isolated interconnect lines. Then in the spirit of design rules, we investigate a multilevel interconnect test structure to avert cha nneling cracks caused by differential thermal expansion. (C) 2000 Elsevier Science Ltd. All rights reserved.