A family of low-power truly modular programmable dividers in standard 0.35-mu m CMOS technology

A truly modular and power-scalable architecture for low-power programmable frequency dividers is presented, The architecture was used in the realizati on of a family of low-power fully programmable divider circuits, which cons ists of a 17-bit UHF divider, an 18-bit L-band divider, and a 12-bit refere nce divider. Key circuits of the architecture are 2/3 divider cells, which share the same logic and the same circuit implementation, The current consu mption of each cell can be determined with a simple power optimization proc edure. The implementation of the 2/3 divider cells is presented, the power optimization procedure is described, and the input amplifiers are briefly d iscussed. The circuits were processed in a standard 0.35 mu m bulk CMOS tec hnology, and work with a nominal supply voltage of 2.2 V, The power efficie ncy of the UHF divider is 0.77 GHz/mW, and of the L-band divider, 0.57 GHz/ mW, The measured input sensitivity is >10 mVrms for the UHF divider, and >2 0 mVrms for the L-band divider.