Investigation on low-voltage low-power silicon bipolar design topology forhigh-speed digital circuits

This paper investigates a bipolar design topology which is suitable to oper ate from a voltage supply well below 1.5 V, while maintaining the ability o f high frequency operation. The topology has been applied in the design of different divide-by-4 circuits, utilizing a 20-GHz 0.6-mu m Si bipolar tech nology. The different versions featured slight modifications in the archite cture of the logic cells and the influence on the frequency and supply volt age range of operation has been investigated. Measurements have shown opera tion from 1.0-V supply voltage and up to 4.2-GHz input frequency to 1.5 V a nd up to 6 GHz. The power consumption is approximately 0.3 mW/latch and 1.2 mW/latch, respectively.