A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADC's

Timing errors in time-interleaved ADC's often generate undesirable spurs, a nd hence, degrade the spurious-free dynamic range (SFDR) of the ADC, In thi s paper, a digital-background calibration technique is proposed to minimize these effects, The proposed technique is based on digital interpolation, w hich estimates the correct output values from the output samples that suffe r from timing errors. Since this technique requires an accurate estimation of the timing errors of the individual channels, a digital-background timin g-error measurement technique is also proposed. Theoretical analysis, as we ll as simulation results, show that the calibration technique can greatly a ttenuate the spurs, and the SFDR can be significantly improved by 20-60 dB, depending on the digital hardware complexity and the ratio of sampling fre quency and signal Frequency. The major advantage of this technique is that all the calibration processes are carried out in the background using digit al circuits, and only slight modification is required on the analog part of the ADC for obtaining a background estimation of the timing errors.