Test-set embedding based on width compression for mixed-mode BIST

We present a new test generator circuit (TGC) for mixed-mode built-in self- test (BIST) that embeds a precomputed deterministic test set T-D in a longe r sequence. The design method employs width compression based on the proper ty of d-compatibles. To demonstrate the feasibility of the TGC design metho ds, we present experimental data for single stuck-at test sets for the ISCA S 85 circuits and full-scan versions of the ISCAS 89 benchmark circuits. We also achieve significant improvement over another recently-proposed mixed- mode TGC design scheme for BIST.