Parasitic extraction methodology for insulated gate bipolar transistors

This paper presents a methodology for extraction of the electrical package parasitics of insulated gate bipolar transistor power modules using simple electrical measurements. Non-idealities of device performance in zero-volta ge and zero-current switching are exploited to obtain the parasitic collect or and emitter inductance. Simple impedance measurements are performed to, extract gate inductance and resistance. The extraction methodology is valid ated by comparing two-dimensional numerical simulation results including pa ckage parasitics with measured data. A close match between the two indicate s the robustness of the extraction procedure.