Deterministic BIST with partial scan

An efficient deterministic BIST scheme based on partial scan chains togethe r with a scan selection algorithm tailored for BIST is presented. The algor ithm determines a minimum number of flipflops to be scannable so that the r emaining circuit has a pipeline-like structure. Experiments show that scann ing less flipflops may even decrease the hardware overhead for the on-chip pattern generator besides the classical advantages of partial scan such as less impact on the system performance and less hardware overhead.