An approach to minimize the test configuration for the logic cells of the Xilinx XC4000 FPGAs family

This paper describes an approach to minimize the number of test configurati ons for testing the logic cells of a RAM-based FPGA taking into account the configurability of such flexible device. The proposed approach concerns th e XILINX 4000 Family. On this example of FPGA, a bottom-up test technique i s first used to generate test configurations for the elementary modules, th en test configurations for a single logic cell, and finally test configurat ions for the m x m array of logic cells. In this bottom-up technique, it is shown that the key point is the minimization of the number of test configu rations for a logic cell. An approach for the logic cell of the XILINX4000 family is then described to define a minimum number of test configurations knowing the test configurations of its logic modules. This approach gives o nly 5 test configurations for the XILINX4000 family while the previous publ ished works concerning Boolean testing of this FPGA family fives 8 or 21 te st configurations.