Japanese chipmakers lower costs with design/process integration, wafer-scale packaging

Authors
Nagahiro, Y
Citation
Y. Nagahiro, Japanese chipmakers lower costs with design/process integration, wafer-scale packaging, SOL ST TECH, 43(7), 2000, pp. 62
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
SOLID STATE TECHNOLOGY
ISSN journal
0038111X → ACNP
Volume
43
Issue
7
Year of publication
2000
Database
ISI
SICI code
0038-111X(200007)43:7<62:JCLCWD>2.0.ZU;2-P