Chromeless phase-shift masks used for sub-100nm SOICMOS transistors

The application of chromeless phase-shift masks to sub-100nm gate length SO I transistor fabrication has achieved considerably enhanced resolution perf ormance compared with alternating aperture while still preserving good proc ess latitudes. The maskmaking process uses a simple, single-step dry etch w ith no minimum geometry features, thus simplifying mask fabrication. In waf er fabrication, using just a 0.6 NA 248nm lithography tool and commercially available resists and antireflection layers, researchers achieved lithogra phy results for k(1) factors down to 0.10 for isolated features and 0.3 for dense features. This corresponds to 40nm (isolated) and 125nm (dense) CDs on the stepper, or lambda/6 and lambda/2 resolutions, respectively. Excelle nt pattern transfer into polysilicon was achieved using a high-density plas ma etch process producing gate features down to 25nm linewidths (k(1) = 0.0 6, or lambda/10 resolution). The net results were sub-100nm gate-length ful ly depleted SOI CMOS transistors with excellent short-channel behavior down to 50nm physical gate lengths.