An integrated etch approach as STI evolves for the 100nm regime

As shallow trench isolation progresses toward the 100nm regime, numerous te chnical and manufacturing problems need to be resolved. The work presented here examines the current process parameter envelope, identifies problem ar eas, and develops an integration scheme that reduces process complexity and cost. The final scheme includes an integrated etch that could process hard mask opening, top corner rounding, and silicon trench etch in one pass. It also provides high-density oxide gap-fill that does not require annealing and can be planarized with direct-polish CMP.