Evidence for ferroelectric border traps near the SrBi2Ta2O9/Si interface through capacitance-voltage measurement

A metal-ferroelectric-semiconductor (MFS) structure has been developed by d epositing SrBi2Ta2O9 (SBT) films directly on n-type (100) Si by pulsed lase r deposition. In the MFS structure, evidence for ferroelectric border traps in the SBT film has been obtained by high-frequency capacitance-voltage (C -V) measurement. When the ramp rate of voltage is higher than 200 mV/s, typ ical ferroelectric C-V hysteresis loops with the counterclockwise direction are obtained in C-V plots. When the ramp rate is lower than 80 mV/s, the f erroelectric hysteresis loops are replaced by the trap-induced ones with th e clockwise direction. This pronounced change results from the fact that mo re and more border traps in SBT can communicate with the underlying Si. The border-trap density at the ramp rate of 10 mV/s is as high as 1.8x10(12) c m(-2). Moreover, the width of the hysteresis loops changes linearly with th e logarithmic decrease in ramp rate, which is consistent with the ferroelec tric border traps communicating with Si by tunneling or a thermally activat ed process. (C) 2000 American Institute of Physics. [S0003-6951(00)03930-9] .