Time-domain macromodel for lossy VLSI interconnects

Authors
Cappuccino, G Cocorullo, G
Citation
G. Cappuccino et G. Cocorullo, Time-domain macromodel for lossy VLSI interconnects, ELECTR LETT, 36(14), 2000, pp. 1207-1208
Citations number
4
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
36
Issue
14
Year of publication
2000
Pages
1207 - 1208
Database
ISI
SICI code
0013-5194(20000706)36:14<1207:TMFLVI>2.0.ZU;2-0
Abstract
A new time-domain model that enables loss effects on the input impedance of on-chip transmission lines during switching transients to be accurately ta ken into account is presented. The model has been specifically developed fo r use in conjunction with MOS macromodels to predict the electrical behavio ur of matched CMOS buffers. It solves the problem of mixed frequency/time d omain analysis by replacing the lines with a lumped time-varying resistor.