Verification methodology for a complex System-on-a-Chip

Citation
A. Higashi et al., Verification methodology for a complex System-on-a-Chip, FUJITSU SCI, 36(1), 2000, pp. 24-30
Citations number
5
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
FUJITSU SCIENTIFIC & TECHNICAL JOURNAL
ISSN journal
00162523 → ACNP
Volume
36
Issue
1
Year of publication
2000
Pages
24 - 30
Database
ISI
SICI code
0016-2523(2000)36:1<24:VMFACS>2.0.ZU;2-7
Abstract
Semiconductor technology has progressed to the point where it is now possib le to implement system-level functions on a single LSI chip. However, tradi tional LSI verification becomes less and less powerful as the scale and com plexity increase. In fact, more than half of the time required to develop a System-on-a-Chip (SOC) is used for function verification. A new verificati on methodology for SOCs should therefore be established. We developed a system-level simulation technology to verify the specificati on and architecture of an SOC and a logic emulation technology to verify th e logic function of an entire SOC. By combining these technologies, we esta blished a powerful verification methodology for an SOC. We applied the veri fication methodology to develop a high-definition MPEG2 decoder LSI for a d igital TV broadcasting system. The LSI was successfully developed on schedu le and worked in the first silicon implementation completely according to t he specifications.