A 2-byte parallel 1.25 Gb/s interconnect I/O interface with self-configurable link and plesiochronous clocking

An I/O transceiver for scalable multiprocessor systems', has been developed with a high parallel bandwidth (1.25 Gb/s x 2-byte) and low latency (7.4 n s). The transceiver performs plesiochronous clocking, and compensates for s kin-effect cable loss and inter-wiring skew across cable connections of 20 m in length. We used a phase-interpolator-based clocking scheme that ensure s a high skew-adjustment resolution (25 ps +/- 5 ps adjustment step) and pl esiochronous clocking and can tolerate slight differences in frequency betw een the incoming and internal reference clocks. A Differential Partial Resp onse Detection (DPRD) receiver has also been developed to ensure a low late ncy equalization for a skin-effect cable loss of up to 10 dB. The receivers are equipped with deskew circuitry to tolerate an inter-wiring skew of up to 6.4 ns for 20 data bits. The data rate, driver output level, and receive r clock phase are adjusted automatically by a logic sequencer called the "B asic control." The sequencer maximizes the data rate and the minimizes powe r consumption without external manual adjustments, and can adapt to a wirin g environment ranging from on-board PCB traces to 20 m twisted-pair cables. We designed a test chip for parallel-link interconnection using a 0.25 mu m CMOS process and confirmed that it was capable of 1.25 Gb/s 2-byte parall el signal transmission over a 20 m AWG 28 twisted-pair cable.